Solid-state imaging device

ABSTRACT

According to one embodiment, a photoelectric converting layer, a charge accumulating layer, and a light collecting unit are provided. The photoelectric converting layer is formed at a back surface side of a semiconductor substrate. The charge accumulating layer is formed at a front surface side of the semiconductor substrate, and accumulates charges photoelectric-converted by the photoelectric converting layer. The light collecting unit makes light incident to the back surface side of the semiconductor substrate to be collected on the photoelectric converting layer not to be incident to the charge accumulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.13/938,616, filed Jul. 10, 2013, which claims the benefit of priorityfrom Japanese Patent Application No. 2013-036349, filed Feb. 26, 2013,the contents of which is incorporated in its entirety.

FIELD

Embodiments described herein relate generally to a solid-state imagingdevice.

BACKGROUND

There is a solid-state imaging device having a global shutter structurein order to avoid rolling shutter distortion in which a subject isobliquely imaged. In the global shutter structure, a charge accumulatingportion is formed separately from a photoelectric converting layer, andall pixels can start an accumulation operation at the same time orexecute a reading operation at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a schematic configuration of asolid-state imaging device according to a first embodiment;

FIG. 2 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure applied to the solid-state imaging deviceof FIG. 1;

FIG. 3 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 2;

FIG. 4 is a cross-sectional view taken along line A1-A2 of FIG. 3;

FIG. 5A is a cross-sectional view illustrating a configuration in whichan impurity diffusion layer of a photoelectric converting layer of FIG.4 is developed in a horizontal direction, and FIG. 5B is a diagramillustrating the potential distribution of the configuration illustratedin FIG. 5A;

FIG. 6 is a timing chart illustrating an operation of components of thetwo-pixel one-cell structure of FIG. 2;

FIG. 7 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure according to a second embodiment;

FIG. 8 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 7;

FIG. 9 is a cross-sectional view taken along line B1-B2 of FIG. 8;

FIG. 10 is a timing chart illustrating an operation of components of thetwo-pixel one-cell structure of FIG. 7;

FIG. 11 is an enlarged timing chart illustrating a period of time from atime t5 to a time t13 of FIG. 10;

FIG. 12 is an enlarged timing chart illustrating a period of time, whichcorresponds to a period of time from a time t5 to a time t13 of FIG. 10,in a two-pixel one-cell structure according to a third embodiment;

FIG. 13A is a block diagram illustrating a schematic configuration of anoutput synthesizing unit applied to the two-pixel one-cell structureaccording to the third embodiment, and FIG. 139 is a block diagramillustrating a schematic configuration of an output synthesizing unitapplied to a two-pixel one-cell structure according to a fourthembodiment;

FIG. 14 is a block diagram illustrating a schematic configuration of amotion detecting unit applied to a two-pixel one-cell structureaccording to a fifth embodiment;

FIG. 15 is a timing chart illustrating an operation of components of atwo-pixel one-cell structure according to a sixth embodiment;

FIG. 16 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure according to a seventh embodiment;

FIG. 17 is a plane view illustrating of the layout structure of thetwo-pixel one-cell structure of FIG. 16;

FIG. 18 is a cross-sectional view taken along line C1-C2 of FIG. 17;

FIG. 19A is a cross-sectional view illustrating a configuration in whichan impurity diffusion layer of a photoelectric converting layer of FIG.18 is developed in a horizontal direction, and FIG. 19B is a diagramillustrating the potential distribution of the configuration illustratedin FIG. 19A;

FIG. 20 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure according to an eighth embodiment;

FIG. 21 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 20; and

FIG. 22 is a cross-sectional view taken along line D1-D2 of FIG. 21.

DETAILED DESCRIPTION

In general, according to one embodiment, a photoelectric convertinglayer, a charge accumulating layer, and a light collecting unit areprovided. The photoelectric converting layer is formed at a back surfaceside of a semiconductor substrate. The charge accumulating layer isformed at a front surface side of the semiconductor substrate, andaccumulates charges photoelectric-converted by the photoelectricconverting layer. The light collecting unit makes light incident to theback surface side of the semiconductor substrate to be collected on thephotoelectric converting layer not to be incident to the chargeaccumulating layer.

A solid-state imaging device according to exemplary embodiments will bedescribed in detail with reference to the accompanying drawings. Thepresent invention is not limited to the following embodiments.

First Embodiment

FIG. 1 is a block diagram illustrating a schematic configuration of asolid-state imaging device according to a first embodiment.

Referring to FIG. 1, the solid-state imaging device includes a pixelarray unit 1. The pixel array unit 1 includes pixels P, which accumulatephotoelectric-converted charges, arranged in the form of a matrix in arow direction RD and a column direction CD. In the pixel P, aphotoelectric converting layer performing photoelectric conversion and acharge accumulating layer accumulating photoelectric-converted chargesmay be separately formed. The charge accumulating layer may have a diodestructure or a CCD structure. The photoelectric converting layer may bedisposed on a back surface side of a semiconductor substrate, and thecharge accumulating layer may be disposed on a front surface side of thesemiconductor substrate. At this time, the photoelectric convertinglayer may at least partially overlap the charge accumulating layer. Inthe pixel array unit 1, a horizontal control line Hlin used for readingcontrol of the pixel P is disposed in the row direction RD, and avertical signal line Vlin transmitting a signal read from the pixel P isdisposed in the column direction CD.

The solid-state imaging device further includes a vertical scanningcircuit 2 that scans the pixel P serving as a reading target in thevertical direction, a load circuit 3 that performs a source followeroperation with the pixel P and reads a signal from the pixel P out tothe vertical signal line Vlin in units of columns, a column analogdigital conversion (ADC) circuit 4 that detects a signal component ofeach pixel P in units of columns by correlated double sampling (CDS), ahorizontal scanning circuit 5 that scans the pixel P serving as areading target in the horizontal direction, a reference voltagegenerating circuit 6 that outputs a reference voltage VREF to the columnADC circuit 4, a timing control circuit 7 that controls a reading timingor an accumulation timing of each pixel P, and a global shutter controlunit 8 that makes all the pixels P to start the accumulation operationat the same time or to execute the reading operation at the same time. Aramp wave may be used as the reference voltage VREF.

As the global reset signal ASSET is rising edge-triggered by the globalshutter control unit 8, charges of the photoelectric converting layer ofeach pixel P are discharged, and as the global, reset signal ASSET isfalling edge-triggered, the photoelectric conversion and the chargeaccumulation operation in the photoelectric converting layer of eachpixel P starts. As a global read signal ARead is rising edge-triggeredby the global shutter control unit 8, charges are read out to the chargeaccumulating layer from the photoelectric converting layer of each pixelP.

As the read operation is scanned in the vertical direction by thevertical scanning circuit 2, the pixel P is selected in the rowdirection RD. As the load circuit 3 performs the source followeroperation with the corresponding pixel P, the signal read out from thepixel P is transferred to the column ADC circuit 4 via the verticalsignal line Vlin. In the reference voltage generating circuit 6, theramp wave is set as the reference voltage VREF and transferred to thecolumn ADC circuit 4. In the column ADC circuit 4, a clock countingoperation is performed until each of the signal level read out from thepixel P and the reset level matches a level of the ramp wave, the signalcomponent of each pixel P is detected by the CDS based on the differencebetween the signal level and the reset level at that time, and an outputsignal S1 is output as a digital signal.

FIG. 2 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure applied to the solid-state imaging deviceof FIG. 1.

Referring to FIG. 2, a cell includes photoelectric converting layers PA1and PA2, charge accumulating layers MA1 and MA2, a detecting transistorTA1, a reset transistor TB1, read transistors TC1 and TC2, global resettransistors TE1 and TE2, and global read transistors TD1 and TD2. Afloating diffusion FD is formed at a connection point among thedetecting transistor TA1, the reset transistor TB1, and the readtransistors TC1 and TC2 as a detection node. Here, photodiodes PD1 andPD2 are formed in the photoelectric converting layers PA1 and PA2,respectively, and diodes MD1 and MD2 are formed in the chargeaccumulating layers MA1 and MA2, respectively.

Here, the photoelectric converting layer PA1, the charge accumulatinglayer MA1, the read transistor TC1, the global reset transistor TE1, andthe global read transistor TD1 may belong to one pixel P of the cell,and the photoelectric converting layer PA2, the charge accumulatinglayer MA2, the read transistor TC2, the global reset transistor TE2, andthe global read transistor TD2 may belong to the other pixel P of thecell. The floating diffusion FD, the detecting transistor TA1 and thereset transistor TB1 are shared by the two pixels P of the cell.

The global reset transistor TE1, the global read transistor TD1 and theread transistor TC1 are connected in series. The photodiode PD1 isconnected to a connection point between the global reset transistor TE1and the global read transistor TD1, and the diode MD1 is connected to aconnection point between the global read transistor TD1 and the readtransistor TC1.

The global reset transistor TE2, the global read transistor TD2 and theread transistor TC2 are connected in series. The photodiode PD2 isconnected to a connection point between the global reset transistor TE2and the global read transistor TD2, and the diode MD2 is connected to aconnection point between the global read transistor TD2 and the readtransistor TC2.

Sources of the read transistors TC1 and TC2, a gate of the detectingtransistor TA1, and a source of the reset transistor TB1 are connectedto the floating diffusion FD.

The global reset signal ARSET is input to gates of the global resettransistors TE1 and TE2, and the global read signal ARead is input togates of the global read transistors TD1 and TD2. Read signals Read1 andRead2 are input to gates of the read transistors TC1 and TC2,respectively, and a reset signal RESET is input to a gate of the resettransistor TB1. A reset potential VReset is input to a drain of thereset transistor TB1, a power potential VDD is input to a drain of thedetecting transistor TA1, and a pixel signal Vsig is output from thesource of the detecting transistor TA1 to the vertical signal line Vlin.

The reset potential VReset may be shared with the power potential VDD.By causing the reset potential VReset to be equal to the power potentialVDD (for example, 2.8 V), the floating diffusion FD can be reset, andthe detecting transistor TA1 can be set to an operation state. Further,by setting the reset potential VReset to 0.2 V to 0.5 V, the floatingdiffusion SD can become a low voltage state, and the detectingtransistor TA1 can be turned off.

As the global reset signal ARSET is rising edge-triggered, the globalreset transistors TE1 and TE2 are turned on, changes are discharged fromthe photodiodes PD1 and PD2 of all the pixels P to the power potentialVDD. As the global reset signal ARSET is falling edge-triggered, theglobal reset transistors TE1 and TE2 are turned off, and the chargeaccumulation operations of the photodiodes PD1 and PD2 of all the pixelsP are started. As the global read signal ARead is applied, the globalread transistors TD1 and TD2 are turned on, in all the pixels P, chargesare simultaneously read out from the photodiodes PD1 and PD2 to thediodes MD1 and MD2.

Thereafter, when the reset signal RESET is rising edge-triggered in astate in which the reset potential VReset has the high level, extracharges, in the floating diffusion FD, generated by a leakage current orthe like are reset as the reset transistor TB1 is turned on. Further, avoltage corresponding to the reset level of the floating diffusion FD isapplied to the gate of the detecting transistor TA1. Here, the detectingtransistor TA1 configures the source follower together with the loadcircuit 3 through the vertical signal line Vlin, the voltage of thevertical signal line Vlin follows the voltage applied to the gate of thedetecting transistor TA1, and the pixel signal Vsig of the reset levelis output to the column ADC circuit 4 via the vertical signal line Vlin.

Then, in the column ADC circuit 4, when the ramp wave is applied as thereference voltage VREF in a state in which the pixel signal Vsig of thereset level is input, the pixel signal Vsig of the reset level iscompared with the ramp wave.

Then, as down-counting is performed until the pixel signal Vsig of thereset level matches the level of the ramp wave, the pixel signal Vsig ofthe reset level is converted into a digital value and then stored.

Next, when the read signal Read1 is rising edge-triggered, the readtransistor TC1 is turned on, charges accumulated in the diode MD1 aretransferred to the floating diffusion FD, a voltage corresponding to thesignal level of the floating diffusion FD is applied to the gate of thedetecting transistor TA1. Here, the detecting transistor TA1 configuresthe source follower together with the load circuit 3 through thevertical signal line Vlin, the voltage of the vertical signal line Vlinfollows the voltage applied to the gate of the detecting transistor TA1,and the output voltage of the signal level is output to the column ADCcircuit 4 via the vertical signal line Vlin as the pixel signal Vsig.

Then, in the column ADC circuit 4, when the ramp wave is applied as thereference voltage VREF in a state in which the output voltage Vsig ofthe signal level is input, the output voltage Vsig of the signal levelis compared with the ramp wave.

Then, as up-counting is now performed until the output voltage Vsig ofthe signal level matches the level of the ramp wave, the differencebetween the output voltage Vsig of the signal level and the outputvoltage Vsig of the reset level is converted into a digital value, andthen the output signal S1 in which the reset level of each cell and withvariation of the detecting transistor Till are removed by the CDSoperation is output.

Next, when the reset signal RESET is rising edge-triggered in a state inwhich the reset potential VReset has the low level, the reset transistorTB1 is turned on, the potential of the floating diffusion FD is set tothe low level. For this reason, the detecting transistor TA1 is turnedoff, and the voltage of the vertical signal line Vlin does not followthe potential of the floating diffusion FD.

Here, as the charge accumulating layers MA1 and MA2 are formed in thephotoelectric converting layers PA1 and PA2, respectively, the chargeaccumulation operation of the photoelectric converting layers PA1 andPA2 of all the pixels P is simultaneously started, and charges aresimultaneously read out the photoelectric converting layers PA1 and PA2of all the pixels P to the charge accumulating layers MA1 and MA2, evenwhile the subject is being moved, rolling shutter distortion in whichthe subject is obliquely imaged can be avoided.

FIG. 3 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 2.

Referring to FIG. 3, a cell CE1 includes the photoelectric convertinglayers PA1 and PA2 and the charge accumulating layers MA1 and MA2. Here,the photoelectric converting layers PA1 and PA2 may be disposed on theback surface side of the semiconductor substrate, and the chargeaccumulating layers MA1 and MA2 may be disposed on the front surfaceside of the semiconductor substrate. The photoelectric converting layersPA1 and PA2 may at least partially overlap the charge accumulatinglayers MA1 and MA2. The microlenses ML1 and ML2 are disposed on thephotoelectric converting layers PA1 and PA2, respectively. Themicrolenses ML1 and ML2 can make light incident to the back surface sideof the semiconductor substrate to be collected on the photoelectricconverting layers PA1 and PA2 not to be incident to the chargeaccumulating layers MA1 and MA2.

Further, the cell CE1 includes gate electrodes GA1, GB1, GC1, GC2, GD1,GD2, GE1, and GE2. The gate electrodes GA1, GB1, GC1, GC2, GD1, GD2,GE1, and GE2 may be disposed on the front surface side of thesemiconductor substrate. The gate electrode GA1 may configure thedetecting transistor TA1, the gate electrode GB1 may configure the resettransistor TB1, the gate electrodes GC1 and GC2 may configure the readtransistors TC1 and TC2, respectively, the gate electrodes GD1 and GD2may configure the global read transistors TD1 and TD2, respectively, andthe gate electrodes GE1 and GE2 may configure the global resettransistors TE1 and TE2, respectively.

An impurity diffusion layer FH7 is formed between the gate electrodesGE1 and GE2 and the gate electrode GA1, an impurity diffusion layer FH4is formed between the gate electrode GE1 and the gate electrode GD1, animpurity diffusion layer FH10 is formed between the gate electrode GD1and the gate electrode GC1, an impurity diffusion layer FH11 is formedbetween the gate electrodes GC1 and GC2 and the gate electrode GB1, anthe impurity diffusion layer FH13 is formed between the gate electrodeGE2 and the gate electrode GD2, and an impurity diffusion layer FH14 isformed between the gate electrode GD2 and the gate electrode GC2. Animpurity diffusion layer FH15 is formed on the side opposite to theimpurity diffusion layer FH7 with the gate electrode GA1 interposedtherebetween. An impurity diffusion layer FH12 is formed on the sideopposite to the impurity diffusion layer FH11 with the gate electrodeGE1 interposed therebetween.

Here, the photoelectric converting layers PA1 and PA2 may be arranged tobe symmetric to each other in the column direction CD centering on thedetecting transistor TA1, and the charge accumulating layers MA1 and MA2may be arranged to be symmetric to each other in the column direction CDcentering on the detecting transistor TA1. The read transistors TC1 andTC2, the global read transistors TD1 and TD2, and the global resettransistors TE1 and TE2 may be arranged to be symmetric to one anotherin the column direction CD centering on the detecting transistor TA1,respectively. The detecting transistor TA1 may be arranged to besurrounded by the read transistors TC1 and TC2, the global readtransistors TD1 and TD2, and the global reset transistors TE1 and TE2.The cells CE1 and CE2 may be arranged to be adjacent to each other in adirection inclined to the column direction CD at 45°.

An interconnection used to transfer the global reset signal ARSET isconnected to the gate electrodes GE1 and GE2, an interconnection used totransfer the global read signal ARead is connected to the gateelectrodes GD1 and GD2, an interconnection used to transfer the resetpotential VReset is connected to the impurity diffusion layer FH12, aninterconnection used to transfer the power potential VDD is connected tothe impurity diffusion layer FH7, an interconnection used to transferthe pixel signal Vsig1 is connected to the impurity diffusion layer.FH15, an interconnection used to transfer the read signal Read1 isconnected to the gate electrode GC1, an interconnection used to transferthe read signal Read2 is connected to the gate electrode GC2, and aninterconnection used to transfer the reset signal RESET is connected tothe gate electrode GB1. The gate electrode GA1 is connected to theimpurity diffusion layer FH11.

Here, since the cells CE1 and CE2 are arranged to be adjacent to eachother in a direction inclined to the column direction CD at 45°, theinterconnection used to transfer the read signals Read1 and Read2 andthe interconnection used to transfer the reset signal RESET can beshared between the cells CE1 and CE2. Thus, the interconnection used totransfer the read signals Read1 and Read2 and the interconnection usedto transfer the reset signal RESET need not be separately disposed inthe cells CE1 and CE2, and thus the number of interconnections can bereduced.

FIG. 4 is a cross-sectional view taken along line A1-A2 of FIG. 3.

Referring to FIG. 4, an impurity diffusion layer FH1 is formed at theback surface side of a semiconductor substrate SB1, and an impuritydiffusion layer FH0 is formed on the uppermost layer of the back surfaceside of the semiconductor substrate SB1. A P well FH5 is formed on thefront surface side of the semiconductor substrate SB1, and a P well FH6is formed in the P well FH5. The P well FH5 may be formed to be higherin impurity concentration than the P well FH6. The gate electrodes GB1,GC1, GD1, and GE1 are formed above the P well FH6. In the P well FH6,the impurity diffusion layer FH4 is formed between the gate electrodesGE1 and GD1, the impurity diffusion layer FH10 is formed between thegate electrodes GD1 and GC1, and the impurity diffusion layer FH11 isformed between the gate electrodes GC1 and GB1. Further, in the P wellFH6, the impurity diffusion layer FH6 is formed at the side opposite tothe impurity diffusion layer FH4 with the gate electrode GE1 interposedtherebetween, and the impurity diffusion layer FH12 is formed at theside opposite to the impurity diffusion layer FH11 with the gateelectrode GB1 interposed therebetween. Impurity diffusion layers FH3 andFH2 are sequentially formed in the depth direction between the impuritydiffusion layer FH4 and FH1. In the P well FH6, impurity diffusionlayers FH9 and FH8 are sequentially formed in the depth direction belowthe impurity diffusion layer FH10. The impurity diffusion layers FH1,FH2, FH3, FH7, FH8, FH9, FH11, and FH12 may have an n type, and theimpurity diffusion layers FH0, FH4, and FH10 may have a p type. Theimpurity diffusion layers FH1, FH2, FH3, FH8, and FH9 may be formed toincrease in the impurity concentration in the described order. Thephotoelectric converting layer PA1 may be arranged to at least partiallyoverlap the charge accumulating layer. MA1. The photoelectric convertinglayer PA1 may be separated from the charge accumulating layer MA1 by theP well FH5.

On the back surface side of the semiconductor substrate SB1, atransparent layer EL1 is formed on the impurity diffusion layer FH0, anda microlens ML1 is formed over the transparent layer. EL1 with a colorfilter FL1 interposed therebetween. A light blocking layer SL1 is buriedin the transparent layer EL1. The transparent layer EL1 may be made oftransparent resin such as acrylic. The light blocking layer SL1 may bemade of metal such as A1. The microlens ML1 may make light incident tothe back surface side of the semiconductor substrate SB1 to be collectedon the photoelectric converting layer PA1 not to be incident to thecharge accumulating layer MA1. The light blocking layer SL1 can blocklight incident to the back surface side of the semiconductor substrateSB1 from being incident to the charge accumulating layer MA1. Thetransparent layer EL1 increases an interval between the photoelectricconverting layer PA1 and the microlens ML1, and thus an incident angleof light incident to the photoelectric converting layer PA1 can bereduced. When the transparent layer EL1 has the thickness of 0.5 um ormore, there is an effect by which light harvesting on the photoelectricconverting layer PA1 is improved.

Here, as the photoelectric converting layer PA1 is arranged to at leastpartially overlap the charge accumulating layer MA1, the size of thepixel P can be reduced while supporting the global shutter structure.Further, as the light blocking layer SL1 is formed at the back surfaceside of the semiconductor substrate SB1, light incident to the backsurface side of the semiconductor substrate SB1 can be prevented frombeing incident to the charge accumulating layer MA1. Furthermore, as thetransparent layer EL1 is formed at the back surface side of thesemiconductor substrate SB1, an incident angle of light incident to thephotoelectric converting layer PA1 can be reduced, and light to becollected on the photoelectric converting layer PA1 can be preventedfrom leaking to the charge accumulating layer MA1. In addition, as theimpurity diffusion layer PH0 is formed on the uppermost layer of theback surface side of the semiconductor substrate SB1, a leakage currentleaking to the charge accumulating layer MA1 can be reduced.

Further, as the P well in the front surface side of the semiconductorsubstrate SB1 has a dual-layer structure, and the P well FH5 separatingthe photoelectric converting layer PA1 from the charge accumulatinglayer MA1 is higher in the impurity concentration than the P well FH6 inwhich a channel is formed, isolation between the photoelectricconverting layer PA1 and the charge accumulating layer MA1 can beimproved. Further, as the P well FH5 is formed, the capacity of thephotoelectric converting layer PA1 and the charge accumulating layer MA1can be increased, the number of saturated electrons can be increased,and charges generated in the boundary between the photoelectricconverting layer PA1 and the charge accumulating layer MA1 can be easilytaken into the photoelectric converting layer PA1.

FIG. 5A is a cross-sectional view illustrating a configuration in whichthe impurity diffusion layer of the photoelectric converting layer ofFIG. 4 is developed in the horizontal direction, and FIG. 5B is adiagram illustrating the potential distribution of the configurationillustrated in FIG. 5A.

Referring to FIG. 5A, the impurity diffusion layers FH1, FH2, and FH3are set to increase in the impurity concentration in the describedorder, and the potential gradient is formed from the back surface sideof the semiconductor substrate SB1 toward the front surface sidethereof. Thus, charges generated at the hack surface side of thephotoelectric converting layer PA1 can be collected at the front surfaceside thereof, and charges can be smoothly transferred from thephotoelectric converting layer PA1 to the charge accumulating layer MA1.

When the photoelectric converting layer PA1 starts to accumulate, as theglobal reset signal. ARSET is rising edge-triggered, extra signalcharges accumulated in the photoelectric converting layer PA1 aredischarged. During the accumulation operation of the photoelectricconverting layer PA1, signal charges are accumulated such that thesignal charges photoelectric-converted by the photoelectric convertinglayer PA1 flow to the impurity diffusion layer FH3 side having the deeppotential, and the signal charge overflowing over the impurity diffusionlayer FH3 are spread to the impurity diffusion layers FH2 and FH1. Atthis lime, the global reset signal ARSET is set to a low voltage of 0.2V to 0.5 V, the global read signal. Aread, the read signal Read1, andthe reset signal RESET are set to 0 V. Alternatively, the global resetsignal. ARSET is set to 0 V, and the global read signal Aread, the readsignal Read1, and the reset signal RESET are set to −1.0 to −0.5 V. As aresult, when intense light is incident to the photoelectric convertinglayer PA1, the photoelectric converting layer PA1 is saturated. At thistime, the saturated or more signal charges flow to the power potentialVDD via the gate electrode GE1, and thus the signal charges overflowingin the photoelectric converting layer PA1 can be prevented from flowingto the charge accumulating layer MA1 (an overflow drain structure).

Further, as the global read signal Aread is rising edge-triggered, thesignal charges accumulated in the photoelectric converting layer PA1 areread out to the charge accumulating layer MA1. At this time, thepotentials of the photoelectric converting layer PA1 and the chargeaccumulating layer MA1 are set to be getting deeper in the order of theimpurity diffusion layer FH1→the impurity diffusion layer FH2→theimpurity diffusion layer FH3→the impurity diffusion layer FH8→theimpurity diffusion layer FH9, and thus the signal charges of thephotoelectric converting layer PA1 can be smoothly and completely readout. The signal charges overflowing from the impurity diffusion layerFH9 of the charge accumulating layer MA1 can be accumulated in the largearea of the impurity diffusion layer FH8. Further, since the impuritydiffusion layer FH8 comes into contact with the impurity diffusion layerFH5, the capacity can be further increased.

Since the potential of the floating diffusion FD is shallow, that is,0.5 V before signal reading of the charge accumulating layer MA1, thefloating diffusion FD is reset by causing the reset potential VReset tobe equal to the power potential VDD and causing the reset signal RESETto be rising edge-triggered. Then, as the read signal Read1 is risingedge-triggered, the signal charges accumulated in the chargeaccumulating layer MA1 are read out. Since the potential of the floatingdiffusion FD is deeper than the potential of the impurity diffusionlayer FH9 of the charge accumulating layer MA1, all the signal chargesof the charge accumulating layer MA1 can be read out. The charges readout to the floating diffusion FD are converted into a voltage by thedetecting transistor TA1 and then output as the pixel signal Vsig1.

Then, by causing the reset potential VReset to be 0.2 to 0.5 V andcausing the reset signal RESET to be rising edge-triggered, the floatingdiffusion FD is set to 0.2 to 0.5 V, and the detecting transistor TA1 isturned off. For example, when the power potential VDD is 2.8 V, an ONvoltage of each gate is set to 3.6 V obtained by increasing the powerpotential. VDD, and thus large signal charges can be output.

FIG. 6 is a timing chart illustrating an operation of the components ofthe two-pixel one-cell structure of FIG. 2.

Referring to FIG. 6, at a time t0, the global reset signal ARSET isrising edge-triggered on all the pixels P at the same time according toa horizontal synchronous signal HD, and signals are read out of thephotoelectric converting layers PA1 and PA2 of all the pixels P anddischarged to the power potential VDD. Then, the global reset signalARSET is falling edge-triggered, and the photoelectric converting layersPA1 and PA2 of all the pixels P start the accumulation operation at thesame time.

At a time t1, reset signals RESET12, RESET34, RESET56, and the like ofall the pixels P and read signals Read1, Read2, Read3, Read4, Read5,Read6, and the like are rising edge-triggered at the same time, and theextra signal charges (a leakage current, a flaw, or the like) remainingin the charge accumulating layers MA1 and MA2 are discharged to thereset potential VReset through the reset transistor TB1.

The reset signal RESET12 is supplied to the pixels P of a first line anda second line, the reset signal RESET34 is supplied to the pixels P of athird line and a fourth line, and the reset signal RESET56 is suppliedto the pixels P of a fifth line and a sixth line. The read signal. Read1is supplied to the pixels P of the first line, the read signal Read2 issupplied to the pixels P of the second line, the read signal Read3 issupplied to the pixels P of the third line, the read signal Read4 issupplied to the pixels P of the fourth line, the read signal Read5 issupplied to the pixels P of the fifth line, and the read signal Read6 issupplied to the pixels P of the sixth line.

At a time t2, as the global read signal ARead is rising edge-triggeredon all the pixels P at the same time, the signal chargesphotoelectric-converted by the photoelectric converting layers PA1 andPA2 and accumulated are read out to the charge accumulating layers MA1and MA2. At this time, “t2-t0” may be given as an accumulation period oftime tacc1. Further, at this time, the vertical synchronous signal isrising edge-triggered, and a frame is switched from F1 to F2.

At a time t3, the reset signal RESET12 is rising edge-triggered, and theextra signal charges (a leakage current, a flaw, or the like) remainingin the floating diffusions FD of the pixels P of the first line and thesecond line are discharged to the reset potential VReset through thereset transistor TB1. At this time, the voltage of the reset potentialVReset may be set to the same voltage as the power potential VDD.

At a time t4, the read signal Read1 is rising edge-triggered, and thesignal charges accumulated in the charge accumulating layer MA1 of thefirst line are read out to the floating diffusion FD. The signal chargesread out to the floating diffusion FD are converted into a voltage bythe detecting transistor TA1 and output as the pixel signal Vsig. Atthis time, it is possible to extract only the image signal component bythe CDS operation for obtaining the difference between the pixel signalVsig of the reset level when the reset signal RESET12 is risingedge-triggered and the pixel signal Vsig of the signal level when theread signal Read1 is rising edge-triggered.

At a time t5, the reset signal RESET12 is rising edge-triggered, and theextra signal charges (a leakage current, a flaw, or the like) remainingin the floating diffusions FD of the pixels P of the first line and thesecond line are discharged to the reset potential VReset through thereset transistor TB1. At this time, the voltage of the reset potentialVReset may be set to the same voltage as the power potential VDD.

At a time t6, the read signal Read2 is rising edge-triggered, and thesignal charges accumulated in the charge accumulating layer MA2 of thesecond line are read out to the floating diffusion FD. The signal levelin which the signal charges read out to the floating diffusion PD areconverted into a voltage by the detecting transistor TA1 is output asthe pixel signal Vsig.

At a time t7, the reset signal RESET12 is falling edge-triggered to 0.5V or less, and the detecting transistor TA1 is turned off.Alternatively, an address transistor may be disposed at the powerpotential VDD side or the vertical signal line Vlin side of thedetecting transistor TA1, and an OFF setting may be performed by turningoff the address transistor.

Similarly, an operation of from the time t3 to the time t7 is executedin the vertical direction for each line, and the signals accumulated inthe charge accumulating layers MA1 and MA2 can be read out on all thepixels P.

FIG. 7 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure according to a second embodiment.

Referring to FIG. 7, a cell includes photoelectric converting layersPA11 and PA12, charge accumulating layers MAA1, MAB1, MAA2, and MAB2, adetecting transistor TA2, a reset transistor TB2, read transistors TCA1,TCB1, TCA2, and TCB2, global reset transistors TE11 and TE12, and globalread transistors TDA1, TDB1, TDA2, and TDB2. A floating diffusion FD isformed at a connection point among the detecting transistor TA2, thereset transistor TB2, and the read transistors TCA1, TCB1, TCA2, andTCB2 as a detection node. Here, photodiodes PD11 and PD12 are formed inthe photoelectric converting layers PA11 and PA12, respectively, anddiodes MDA1, MDB1, MDA2, and MDB2 are formed in the charge accumulatinglayers MAA1, MAB1, MAA2, and MAB2, respectively.

Here, the photoelectric converting layer PA11, the charge accumulatinglayers MAA1 and MAB1, the read transistors TCA1 and TCB1, the globalreset transistor TE11, and the global read transistors TDA1 and TDB1 maybelong to one pixel P of the cell, and the photoelectric convertinglayer PA12, the charge accumulating layers MAA2 and MAB2, the readtransistors TCA2 and TCB2, the global reset transistor TE12, and theglobal read transistors TDA2 and TDB2 may belong to the other pixel P ofthe cell. The floating diffusion FD, the detecting transistor TA2, andthe reset transistor TB2 are shared by the two pixels P of the cell.

The global read transistor TDA1 and the read transistor TCA1 areconnected in series, the global read transistor TDB1 and the readtransistor TCB1 are connected in series, and the series circuits areconnected to the global reset transistor TE11 in parallel. Thephotodiode PD11 is connected to a connection point among the globalreset transistor TE11 and the global read transistors TDA1 and TDB1, andthe diode MDA1 is connected to a connection point between the globalread transistor TDA1 and the read transistor TCA1.

The global read transistor TDA2 and the read transistor TCA2 areconnected in series, the global read transistor TDB2 and the readtransistor TCB2 are connected in series, and the series circuits areconnected to the global reset transistor TE12 in parallel. Thephotodiode PD12 is connected to a connection point among the globalreset transistor TE12 and the global read transistors TDA2 and TDB2, andthe diode MDA2 is connected to a connection point between the globalread transistor TDA2 and the read transistor TCA2.

Sources of the read transistors TCA1, TCB1, TCA2, and TCB2, a gate ofthe detecting transistor TA2, and a source of the reset transistor TB2are connected to the floating diffusion FD.

A global reset signal. ARSET is input to gates of the global resettransistors TE11 and TE12, a global read signal AReadA is input to gatesof the global read transistors TDA1 and TDA2, and a global read signalAReadB is input to gates of the global read transistors TDB1 and TDB2.Read signals Read1A, Read1B, Read2A, and Read2B are input to gates ofthe read transistors TCA1, TCB1, TCA2, and TCB2, respectively, and areset signal RESET is input to a gate of the reset transistor TB2. Areset potential VReset is input to a drain of the reset transistor TB2,a power potential VDD is input to a drain of the detecting transistorTA2, and a pixel signal Vsig is output from a source of the detectingtransistor TA2 to the vertical signal line Vlin.

Here, when a plurality of charge accumulating layers MAA1, MAB1, MAA2,and MAB2 are formed in parallel for every photoelectric convertinglayers PA1 and PA2, the number of saturated electrons can be increasedto twice, two signals that differ in an accumulation period of time canbe obtained, and thus the dynamic range can be increased. Further, adifference is brought about between the accumulation periods of time,charges are read out from the photoelectric converting layer PA11 to thecharge accumulating layers MAA1 and MAB1, and a differential output isobtained by signal processing, and thus only a signal of a movingsubject can be obtained.

FIG. 8 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 7.

Referring to FIG. 8, a cell CE11 includes the photoelectric convertinglayers PA11 and PA12 and the charge accumulating layers MAA1, MAB1,MAA2, and MAB2. Here, the photoelectric converting layers PA11 and PA12may be disposed on the back surface side of the semiconductor substrate,and the charge accumulating layers MAA1, MAB1, MAA2, and MAB2 may bedisposed on the front surface side of the semiconductor substrate. Thephotoelectric converting layers PA11 and PA12 may at least partiallyoverlap the charge accumulating layers MAA1, MAB1, MAA2, and MAB2.Microlenses ML11 and ML12 are disposed on the photoelectric convertinglayers PA11 and PA12, respectively. The microlenses ML11 and ML12 maymake light incident to the back surface side of the semiconductorsubstrate to be collected on the photoelectric converting layers PA11and PA12 not to be incident to the charge accumulating layers MAA1,MAB1, MAA2, and MAB2.

Further, the cell CE11 includes gate electrodes GA2, GB2, GCA1, GCB1,GCA2, GCB2, GDA1, GDA2, GDB1, GDB2, GE11, and GE12. The gate electrodesGA2, GB2, GCA1, GCB1, GCA2, GCB2, GDA1, GDA2, GDB1, GDB2, GE11, and GE12may be disposed on the front surface side of the semiconductorsubstrate. The gate electrode GA2 may configure the detecting transistorTA2, the gate electrode GB2 may configure the reset transistor TB2, thegate electrodes GCA1, GCB1, GCA2, and GCB2 may configure the readtransistors TCA1, TCB1, TCA2, and TCB2, respectively, the gateelectrodes GDA1, GDB1, GDA2, and GDB2 may configure the global readtransistors TDA1, TDB1, TDA2, and T2132, respectively, and the gateelectrode GE11 and GE12 may configure the global reset transistors TE11and TE12, respectively.

An impurity diffusion layer FH24 is formed between the gate electrodeGE11 and the gate electrode GDA1, GDB1, an impurity diffusion layer FH30is formed between the gate electrode GDA1 and the gate electrode GCA1,an impurity diffusion layer FH35 is formed between the gate electrodeGDB1 and the gate electrode GCB1, an impurity diffusion layer FH33 isformed between the gate electrode GE12 and the gate electrodes GDA2 andGDB2, an impurity diffusion layer FH36 is formed between the gateelectrode GDA2 and the gate electrode GCA2, an impurity diffusion layerFH34 is formed between the gate electrode GDB2 and the gate electrodeGCB2, and an impurity diffusion layer FH31 is formed between the gateelectrodes GCA1, GCB1, GCA2, and GCB2 and the gate electrode GB2. Animpurity diffusion layer FH27 is formed at the side opposite to theimpurity diffusion layer FH24 with the gate electrode GE11 interposedtherebetween, an impurity diffusion layer FH37 is formed at the sideopposite to the impurity diffusion layer FH33 with the gate electrodeGE12 interposed therebetween, and an impurity diffusion layer FH32 isformed at the side opposite to the impurity diffusion layer FH31 withthe gate electrode GB2 interposed therebetween. Impurity diffusionlayers FH38 and FH39 are formed at both sides of the gate electrode GA2.

Here, the photoelectric converting layers PA11 and PA12 may be arrangedto be symmetrical to each other in the column direction CD centering onthe detecting transistor TA2, and the charge accumulating layers MAA1and MAB1 and the charge accumulating layers MAA2 and MAB2 may bearranged to be symmetrical to each other in the column direction CDcentering on the detecting transistor TA2, respectively. The readtransistors TCA1, TCB1, TCA2, and TCB2, the global read transistorsTDA1, TDB1, TDA2, and TDB2, and the global reset transistors TE11 andTE12 may be arranged to be symmetrical to each other in the columndirection CD centering on the detecting transistor TA2, respectively.The gate electrodes GCA1, GCB1, GDA1, and GDB1 may be arranged on sidesof a rectangle, respectively, and the gate electrodes GB2 and GE11 maybe arranged at facing diagonal positions of a rectangle, respectively.The gate electrodes GCA2, GCB2, GDA2, and GDB2 may be arranged on sidesof a rectangle, respectively, and the gate electrodes GB2 and GE12 maybe arranged at facing diagonal positions of a rectangle, respectively.The cells CE11 and CE12 may be arranged to be adjacent to each other ina direction inclined to the column direction CD at 45°.

An interconnection used to transfer the global reset signal ARSET isconnected to the gate electrodes GE11 and GE12, an interconnection usedto transfer the global read signal AReadA is connected to the gateelectrodes GDA1 and GDA2, an interconnection used to transfer the globalread signal AReadB is connected to the gate electrodes GDB1 and GDB2, aninterconnection used to transfer the reset potential VReset is connectedto the impurity diffusion layer FH32, an interconnection used totransfer the power potential VDD is connected to the impurity diffusionlayers FH27 and FH39, an interconnection used to transfer the pixelsignal. Vsig2 is connected to the impurity diffusion layer FH38, aninterconnection used to transfer the read signal Read1A is connected tothe gate electrode GCA1, an interconnection used to transfer the readsignal. Read1B is connected to the gate electrode GCB1, aninterconnection used to transfer the read signal Read2A is connected tothe gate electrode GCA2, an interconnection used to transfer the readsignal Read2B is connected to the gate electrode GCB2, and aninterconnection used to transfer the reset signal RESET is connected tothe gate electrode GB2. The gate electrode GA2 is connected to theimpurity diffusion layer FH31.

Here, since the cells CE11 and CE12 are arranged to be adjacent to eachother in a direction inclined to the column direction CD at 45°, theinterconnection used to transfer the read signals Read1A, Read1B,Read2A, and Read2B and the interconnection used to transfer the resetsignal RESET can be shared between the cells CE11 and CE12. Thus, theinterconnection used to transfer the read signals Read1A, Read1B,Read2A, and Read2B and the interconnection used to transfer the resetsignal RESET need not be separately disposed in the cells CE11 and CE12,and thus the number of interconnections can be reduced.

FIG. 9 is a cross-sectional view taken along line B1-B2 of FIG. 8.

Referring to FIG. 9, an impurity diffusion layer FH21 is formed at theback surface side of a semiconductor substrate SB2, and an impuritydiffusion layer FH20 is formed on the uppermost layer of the backsurface side of the semiconductor substrate SB2. A P well FH25 is formedon the front surface side of the semiconductor substrate SB2, and a Pwell FH26 is formed in the P well FH25. The P well FH25 may be formed tobe higher in impurity concentration than the P well FH26. The gateelectrodes GB2, GCA1, GDA1, and GE11 are formed above the P well FH26.In the P well FH26, the impurity diffusion layer FH21 is formed betweenthe gate electrodes GE11 and GDA1, the impurity diffusion layer PH30 isformed between the gate electrodes GDA1 and GCA1, and the impuritydiffusion layer FH31 is formed between the gate electrodes GCA1 and GB2.Further, in the P well FH26, the impurity diffusion layer FH26 is formedat the side opposite to the impurity diffusion layer FH24 with the gateelectrode GE11 interposed therebetween, and the impurity diffusion layerFH32 is formed at the side opposite to the impurity diffusion layer FH31with the gate electrode GB2 interposed therebetween. Impurity diffusionlayers FH23 and FH22 are sequentially formed in the depth directionbetween the impurity diffusion layers FH24 and FH21. In the P well FH26,impurity diffusion layers FH29 and FH28 are sequentially formed in thedepth direction below the impurity diffusion layer FH30. The impuritydiffusion layers FH21, FH22, FH23, FH27, FH28, FH29, FH31, and FH32 mayhave an n type, and the impurity diffusion layers FH20, FH24, and FH30may have a p type. The impurity diffusion layers FH21, FH22, and FH23are formed to increase in the impurity concentration in the describedorder. The impurity diffusion layers FH29 and FH28 are formed toincrease in the impurity concentration in the described order. Thephotoelectric converting layer PA11 may be arranged to at leastpartially overlap the charge accumulating layer MAA1. The photoelectricconverting layer PA11 may be separated from the charge accumulatinglayer MAA1 by the P well FH25.

On the back surface side of the semiconductor substrate SB2, thetransparent layer EL11 is formed on the impurity diffusion layer FH20,and a microlens ML11 is formed over the transparent layer EL11 with acolor filter FL11 interposed therebetween. The light blocking layer SL11is buried in the transparent layer EL11. The microlens ML11 may makelight incident to the back surface side of the semiconductor substrateSB2 to be collected on the photoelectric converting layer PA11 not to beincident to the charge accumulating layer MAA1. The light blocking layerSL11 can block light incident to the back surface side of thesemiconductor substrate SB2 from being incident to the chargeaccumulating layer MAA1. The transparent layer EL11 increase an intervalbetween the photoelectric converting layer PA11 and the microlens ML11,and thus an incident angle of light incident to the photoelectricconverting layer PA11 can be reduced.

Here, as the photoelectric converting layer PA11 is arranged to at leastpartially overlap the charge accumulating layer MAA1, the size of thepixel P can be reduced while supporting the global shutter structure.Further, as the light blocking layer SL11 is formed at the back surfaceside of the semiconductor substrate SB2, light incident to the backsurface side of the semiconductor substrate SB2 can be prevented frombeing incident to the charge accumulating layer MAA1. Furthermore, asthe transparent layer EL11 is formed at the back surface site of thesemiconductor substrate SB2, an incident angle of light incident to thephotoelectric converting layer PA11 can be reduced, and light to becollected on the photoelectric converting layer PA11 can be preventedfrom leaking to the charge accumulating layer MAA1. In addition, as theimpurity diffusion layer. FH20 is formed on the uppermost layer of theback surface side of the semiconductor substrate SB2, a leakage currentleaking to the charge accumulating layer MAA1 can be reduced.

Further, as the P well in the front surface side of the semiconductorsubstrate SB2 has the dual-layer structure, and the P well FH25separating the photoelectric converting layer PA11 from the chargeaccumulating layer MAA1 is higher in the impurity concentration than theP well FH26 in which a channel is formed, isolation between thephotoelectric converting layer PA11 and the charge accumulating layerMAA1 can be improved. Further, as the P well FH25 is formed, thecapacity of the photoelectric converting layer PA11 and the chargeaccumulating layer MAA1 can be increased, the number of saturatedelectrons can be increased, and charges generated in the boundarybetween the photoelectric converting layer PALL and the chargeaccumulating layer MAA1 can be easily taken into the photoelectricconverting layer PA11.

The potential distribution of the impurity diffusion layers of thephotoelectric converting layer and the charge accumulating layer of FIG.9 is the same as in FIG. 5B. Here, the impurity diffusion layers FH21,FH22, and FH23 are set to increase in the impurity concentration in thedescribed order, and the potential gradient is formed from the backsurface side of the semiconductor substrate SB2 toward the front surfaceside thereof. Thus, charges generated at the back surface side of thephotoelectric converting layer PA11 can be collected at the frontsurface side thereof, and charges can be smoothly transferred from thephotoelectric converting layer PA11 to the charge accumulating layerMAA1.

FIG. 10 is a timing chart illustrating an operation of the components ofthe two-pixel one-cell structure of FIG. 7.

Referring to FIG. 10, at a time t0, the global reset signal ARSET isrising edge-triggered on all the pixels P at the same time according toa horizontal synchronous signal HD, and signals are read out of thephotoelectric converting layers PA1 and PA2 of all the pixels P anddischarged to the power potential VDD. Then, the global reset signalARSET is falling edge-triggered, and the photoelectric converting layersPA1 and PA2 of all the pixels P start the accumulation operation at thesame time.

At a time t1, reset signals RESET12, RESET34, RESET56, and the like ofall the pixels P and read signals Read1A, Read2A, Read3A, Read4A, andthe like is rising edge-triggered at the same time, and the extra signalcharges (a leakage current, a flaw, or the like) remaining in the chargeaccumulating layers MAA1 and MAA2 are discharged to the reset potentialVReset through the reset transistor TB2.

The read signal Read1A is supplied to the charge accumulating layersMAA1 of the pixels P of the first line, the read signal Read2A issupplied to the charge accumulating layers MAA2 of the pixels P of thesecond line, the read signal Read3A is supplied to the chargeaccumulating layers MAA1 of the pixels P of the third line, and the readsignal Read4A is supplied to the charge accumulating layers MAA2 of thepixels P of the fourth line.

At a time t2, the global read signal AReadA is rising edge-triggered onall the pixels P at the same time, the signal chargesphotoelectric-converted by the photoelectric converting layers PA11 andPA12 and accumulated are read out to the charge accumulating layers MAA1and MAA2. At this time, “t2-t0” may be given as an accumulation periodof time tacc11.

At a time t3, reset signals RESET12, RESET34, RESET56, and the like ofall the pixels P and read signals Read1B, Read2E, Read3B, Read4B, andthe like is rising edge-triggered at the same time, and the extra signalcharges (a leakage current, a flaw, or the like) remaining in the chargeaccumulating layers MAB1 and MAB2 are discharged to the reset potentialVReset through the reset transistor TB2.

The read signal Read1B is supplied to the charge accumulating layersMAB1 of the pixels P of the first line, the read signal Read2B issupplied to the charge accumulating layers MAB2 of the pixels P of thesecond line, the read signal Read3B is supplied to the chargeaccumulating layers MAB1 of the pixels P of the third line, and the readsignal Read4A is supplied to the charge accumulating layers MAB2 of thepixels P of the fourth line.

At a time t4, the global read signal AReadB is rising edge-triggered onall the pixels P at the same time, and the signal chargesphotoelectric-converted by the photoelectric converting layers PA11 andPA12 and accumulated are read out to the charge accumulating layers MAB1and MAB2. At this time, “t2-t4” may be given as an accumulation periodof time tacc12. Further, at this time, the vertical synchronous signalis rising edge-triggered, and a frame is switched from F1 to F2.

At a time t5, the reset signal RESET12 is rising edge-triggered, and theextra signal charges (a leakage current, a flaw, or the like) remainingin the floating diffusions FD of the pixels P of the first line and thesecond line are discharged to the reset potential VReset through thereset transistor TB2. At this time, the voltage of the reset potentialVReset may be set to the same voltage as the power potential VDD.

At a time t6, the read signal Read1A is rising edge-triggered, and thesignal charges accumulated in the charge accumulating layer MAA1 of thefirst line are read out to the floating diffusion FD. The signal chargesread out to the floating diffusion FD are converted into a voltage bythe detecting transistor TA2 and output as the pixel signal Vsig. Atthis time, it is possible to extract only the image signal component bythe CDS operation for obtaining the difference between the pixel signalVsig of the reset level when the reset signal RESET12 is risingedge-triggered and the pixel signal Vsig of the signal level when theread signal Read1 is rising edge-triggered.

At a time t7, the reset signal RESET12 is rising edge-triggered, and theextra signal charges (a leakage current, a flaw, or the like) remainingin the floating diffusions FD of the pixels P of the first line and thesecond line are discharged to the reset potential VReset through thereset transistor TB2. At this time, the voltage of the reset potentialVReset may be set to the same voltage as the power potential VDD.

At a time t8, the read signal Read1B is rising edge-triggered, and thesignal charges accumulated in the charge accumulating layer MAB1 of thefirst line are read out to the floating diffusion FD. The signal chargesread out to the floating diffusion FD are converted into a voltage bythe detecting transistor TA2 and then output as the pixel signal Vsig ofthe signal level.

Similarly, at a time t9 to a time t12, the same operation is executed,and the signal charges accumulated in the charge accumulating layersMAA2 and MAB2 of the second line are read out.

At a time t13, the reset signal RESET12 is falling edge-triggered to 0.5V or less, and the detecting transistor TA2 is turned off.Alternatively, an address transistor may be disposed at the powerpotential VDD side or the vertical signal line Vlin side of thedetecting transistor TA2, and an OFF setting may be performed by turningoff the address transistor.

Similarly, an operation during the period of the time from the time t5to the time t13 is executed in the vertical direction for each line, andthe signals accumulated in the charge accumulating layers MAA1, MAB1,MAA2, and MAB2 can be read out on all the pixels P.

In the embodiment illustrated in FIG. 10, during the accumulation periodof time Tacc1 of the frame F1, the accumulation operation of thephotoelectric converting layers PA11 and PA12 is executed twice (theaccumulation period of time tacc11 and the accumulation period of timetacc12). The ratio of the two accumulation period of times tacc11 andtacc11 may be freely set. When the accumulation period of times tacc11and tacc11 may be equal to each other, the signal which is twice as muchas the saturated signal amount of the photoelectric converting layersPA11 and PA12 can be obtained.

FIG. 11 is an enlarged timing chart illustrating the period of time fromthe time t5 to the time t13 of FIG. 1C).

Referring to FIG. 11, at the time t5, the reset signal. RESET12 isrising edge-triggered, and the extra signal charges (a leakage current,a flaw, or the like) remaining in the floating diffusions ED of thepixels P of the first line and the second line are discharged to thereset potential VReset through the reset transistor TB2. Then, the pixelsignal Vsig of the reset level is compared with the reference voltageVREF, and down-counting is performed until the pixel signal Vsig of thereset level matches the reference voltage VREF.

At the time t6, the read signal Read1A is rising edge-triggered, and thesignal charges accumulated in the charge accumulating layer MAA1 of thefirst line are read out to the floating diffusion FD. Then, the pixelsignal Vsig of the signal level is compared with the reference voltageVREF, and up-counting is now performed until the pixel signal Vsig ofthe signal level matches the level of the reference voltage VREF, andthus the difference between the pixel signal Vsig of the signal leveland the pixel signal Vsig of the reset level is converted into a digitalvalue of only the image signal component.

At the time t7, the counting result is not reset, and the reset signalRESET12 is rising edge-triggered, and thus the extra signal charges (aleakage current, a flaw, or the like) remaining in the floatingdiffusions FD of the pixels P of the first line and the second line aredischarged to the reset potential VReset through the reset transistorTB2. Then, the pixel signal Vsig of the reset level is compared with thereference voltage VREF, and down-counting is performed until the pixelsignal Vsig of the reset level matches the level of the referencevoltage VREF.

At the time t8, the read signal Read1B is rising edge-triggered, and thesignal charges accumulated in the charge accumulating layer MAB1 of thefirst line are read out to the floating diffusion FD. Then, the pixelsignal Vsig of the signal level is compared with the reference voltageVREF, up-counting is now performed until the pixel signal Vsig of thesignal level matches the level of the reference voltage VREF, and thusthe difference between the pixel signal Vsig of the signal level and thepixel signal Vsig of the reset level is converted into a digital valueand output as the output signal OUT1. The output signal OUT1 is anaddition value of the signals of the charge accumulating layers MAA1 andMAB1, and the signal which is twice as much as the saturation amount ofthe photoelectric converting layer PA11 can be obtained (a horizontalperiod H1).

During the period of time from the time t9 to the time t12, the sameoperation as during the period of time from the time t5 to the time t8is performed on the pixels P of the second line. Thus, an output signalOUT2 can be obtained, and the saturation signal which is twice as muchas the photoelectric converting layer PA12 can be achieved (a horizontalperiod H2).

FIG. 12 is an enlarged timing chart illustrating a period of time, whichcorresponds to the period of time from the time t5 to the time t13 ofFIG. 10, in a two-pixel one-cell structure according to a thirdembodiment. The embodiment illustrated in FIG. 11 has been described inconnection with the method in which the signals of the chargeaccumulating layers MAA1 and MAB1 are added and output, but anembodiment illustrated in FIG. 12 will be described in connection with amethod of separately outputting the signals of the charge accumulatinglayers MAA1 and MAB1.

Referring to FIG. 12, an output signal OUT11 of the charge accumulatinglayer MAA1 is held in a latch circuit R1. An output signal OUT12 of thecharge accumulating layer MAB1 is held in a latch circuit R2. When thehorizontal period H1 switches to the horizontal period H2, the valuesheld in the latch circuits R1 and R2 are input to line memories LM1 andLM2, respectively. Then, the values are sequentially read out at thesame time by a next horizontal synchronous signal, and then signalprocessing for the wide dynamic range is executed.

For example, a digital gain according to a difference in the length ofthe accumulation period of time may be multiplied so that the twosignals can have the same signal amount, and synthesizing may beperformed so that the two signals can be linear. A ratio tacc12/tacc11of the accumulation periods of time may be set to 1/4, 1/8, 1/16, 1/32,or the like. At this time, a linear inclination is obtained bymultiplying the signal of the accumulation period of time tacc12 by 4,8, 16, and 32 as the digital gain. When the signal of the accumulationperiod of time tacc11 is saturated, switching to the signal obtained bymultiplying the signal of the accumulation period of time tacc12 by thegain is performed, and the signal is output. As a result, the signal inwhich the dynamic range is increased by 4, 8, 16, and 32 times can beobtained.

FIG. 13A is a block diagram illustrating a schematic configuration of anoutput synthesizing unit applied to the two-pixel one-cell structureaccording to the third embodiment, and FIG. 13B is a block diagramillustrating a schematic configuration of an output synthesizing unitapplied to a two-pixel one-cell structure according to a fourthembodiment.

Referring to FIG. 13A, the signals from the charge accumulating layersMAA1 and MAB1 may be not added by a counter but stored in the individualline memories as illustrated in FIG. 12, and then a twofold saturationsignal may be obtained by adding the signals read from the line memoriesthrough a digital adding circuit 11.

Referring to FIG. 13B, for example, when the ratio of the accumulationperiods of time tacc11 and tacc12 is set to 16:1, the output signal ofthe charge accumulating layer MAB1 is multiplied by 16 by a multiplier12, and then the signal obtained by multiplying the output signal of thecharge accumulating layer MAB1 by 16 is compared with the output signalof the charge accumulating layer MAA1 through a comparing circuit 13. Atthis time, before the output of the charge accumulating layer MAA1 issaturated, a threshold value may be set so that the output of the chargeaccumulating layer MAA1 can be set. When the output of the chargeaccumulating layer MAA1 has a level of the set threshold value or more,the output of the charge accumulating layer MAA1 is compared to thesignal obtained by multiplying the output of the charge accumulatinglayer MAB1 by 16. When the signal obtained by multiplying the output ofthe charge accumulating layer MAB1 by 16 is larger than the output ofthe charge accumulating layer. MAA1, the signal obtained by multiplyingthe output of the charge accumulating layer. MAB1 by 16 is selected by aswitch 14, and thus a 14-bit enlarged signal having a linear dynamicrange can be obtained.

FIG. 14 is a block diagram illustrating a schematic configuration of amotion detecting unit applied to a two-pixel one-cell structureaccording to a fifth embodiment.

Referring to FIG. 14, in a motion detecting mode, it is determinedwhether or not a moving object is included in the subject based on adifference between two signals that differ from each other in a shootingtime.

For example, when the accumulation periods of time tacc11 and tacc12 areequal to each other, it is possible to extract only an edge signal of amoved subject by calculating a difference between the signals from thecharge accumulating layers MAA1 and MAB1 through a subtractor 21. Anabsolute value of the difference between the signals is calculated by anabsolute value calculating unit 22, and then input to a motiondetermining unit 24. The motion determining unit 24 counts the number ofsignals larger than a level set by a threshold value setting unit 23,and when the counted number is larger than the set threshold value, itcan be determined that there is a moved subject.

FIG. 15 is a Liming chart illustrating an operation of components of atwo-pixel one-cell structure according to a sixth embodiment.

Referring to FIG. 15, at a time t20, a pulse is added to the globalreset signal ARSET of FIG. 10. As a result, a time difference can be setbetween the accumulation period of time tacc11 and the accumulationperiod of time tacc12, and the accuracy of motion detection can beimproved. Particularly, for a slowly moving subject, a lengthy timedifference may be set between the accumulation period of time tacc11 andthe accumulation period of time tacc12, and the detection capability canbe improved.

FIG. 16 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure according to a seventh embodiment.

Referring to FIG. 16, a cell includes photoelectric converting layersPA21 and PA22, charge accumulating layers MA21 and MA22, a detectingtransistor TA3, a reset transistor TB3, read transistors TC21 and TC22,global reset transistors TE21 and TE22, and global read gates TD21 andTD22. A floating diffusion FD is formed at a connection point among thedetecting transistor TA3, the reset transistor TB3, and the readtransistors TC21 and TC22 as a detection node. Here, the photodiodesPD21 and PD22 are formed in the photoelectric converting layers PA21 andPA22, respectively, and the charge coupling layers MD21 and MD22 areformed in the charge accumulating layers MA21 and MA22, respectively.

Here, the photoelectric converting layer PA21, the charge accumulatinglayer MA21, the read transistor TC21, the global reset transistor TE21,and the global read gate TD21 may belong to one pixel. P of the cell,and the photoelectric converting layer PA22, the charge accumulatinglayer MA22, the read transistor TC22, the global reset transistor TE22,and the global read gate TD22 may belong to the other pixel P of thecell. The floating diffusion FD, the detecting transistor TA3, and thereset transistor TB3 are shared by the two pixels P of the cell.

The global reset transistor TE21, the global read gate TD21, and theread transistor TC21 are connected in series. The photodiode PD21 isconnected to a connection point between the global reset transistor TE21and the global read gate TD21, and the charge coupling layer MD21 iscoupled to the global read gate TD21.

The global reset transistor TE22, the global read gate TD22, and theread transistor TC22 are connected in series. The photodiode PD22 isconnected to a connection point between the global reset transistor TE22and the global read gate TD22, and the charge coupling layer MD22 iscoupled to the global read gate TD22.

Source of the read transistors TC21 and TC22, a gate of the detectingtransistor TA3, and a source of the reset transistor TB3 are connectedto the floating diffusion PD.

The global reset signal ARSET is input to gates of the global resettransistors TE21 and TE22, and the global read signal ARead is input tothe global read gates TD21 and TD22. The read signals Read1 and Read2are input to gates of the read transistors TC21 and TC22, respectively,and the reset signal RESET is input to a gate of the reset transistorTB3. The reset potential VReset is input to a drain of the resettransistor TB3, the power potential VDD is input to a drain of thedetecting transistor TA3, and the pixel signal Vsig is output from asource of the detecting transistor. TA31 to the vertical signal lineVlin.

Here, the charge accumulating layers MA21 and MA22 are formed for everyphotoelectric converting layers PA21 and PA22, the charge accumulationoperations of the photoelectric converting layers PA21 and PA22 of allthe pixels P are simultaneously started, and charges are simultaneouslyread out from the photoelectric converting layers PA21 and PA22 of allthe pixels P to the charge accumulating layers MA21 and MA22. Thus, evenwhile the subject is being moved, rolling shutter distortion in whichthe subject is obliquely imaged can be avoided.

FIG. 17 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 16.

Referring to FIG. 17, a cell CE21 includes the photoelectric convertinglayers PA21 and PA22 and the charge accumulating layers MA21 and MA22.Here, the photoelectric converting layers PA21 and PA22 may be disposedon the back surface side of the semiconductor substrate, and the chargeaccumulating layers MA21 and MA22 may be disposed on the front surfaceside of the semiconductor substrate. The photoelectric converting layersPA21 and PA22 may at least partially overlap the charge accumulatinglayers MA21 and MA22. Microlenses ML21 and ML22 are disposed on thephotoelectric converting layers PA21 and PA22, respectively. Themicrolenses ML21 and ML22 may make light incident to the back surfaceside of the semiconductor substrate to be collected on the photoelectricconverting layers PA21 and PA22 not to be incident to the chargeaccumulating layers MA21 and MA22.

Further, the cell CE21 includes gate electrodes GA3, GB3, GC3, GC4, GD3,GD4, GE3, and GE4. The gate electrodes GA3, GB3, GC3, GC4, GD3, GD4,GE3, and GE4 may be disposed on the front surface side of thesemiconductor substrate. The gate electrode GA3 may configure thedetecting transistor TA3, the gate electrode GB3 may configure the resettransistor TB3, the gate electrodes GC3 and GC4 may configure the readtransistors TC21 and TC22, respectively, the gate electrodes GD3 and GD4may configure the global read gates TD21 and TD22, respectively, and thegate electrodes GE3 and GE4 may configure the global reset transistorsTE21 and TE22, respectively.

The impurity diffusion layer FH47 is formed between the gate electrodesGE3 and GE4 and the gate electrode GA3, the impurity diffusion layerFH44 is formed between the gate electrode GE3 and the gate electrodeGD3, the impurity diffusion layer FH46 is formed between the gateelectrode GD3 and the gate electrode GC3, the impurity diffusion layerFH51 is formed between the gate electrodes GC3 and GC4 and the gateelectrode GB3, the impurity diffusion layer FH53 is formed between thegate electrode GE4 and the gate electrode GD4, and the impuritydiffusion layer FH46 is formed between the gate electrode GD4 and thegate electrode GC4. An impurity diffusion layer FH57 is formed at theside opposite to the impurity diffusion layer FH47 with the gateelectrode GA3 interposed therebetween, and an impurity diffusion layerFH52 is formed at the side opposite to the impurity diffusion layer FH51with the gate electrode GB3 interposed therebetween. Impurity diffusionlayers FH48, FH49, and FH50 are formed below the gate electrode GD3, andimpurity diffusion layers FH54, FH55, and FH56 are formed below the gateelectrode GD4.

Here, the photoelectric converting layers PA21 and PA22 may be arrangedto be symmetric to each other in the column direction CD centering onthe detecting transistor TA3, and the charge accumulating layers MA21and MA22 may be arranged to be symmetric to each other in the columndirection CD centering on the detecting transistor TA3. The readtransistors TC21 and TC22, the global read gates TD21 and TD22, and theglobal reset transistors TE21 and TE22 may be arranged to be symmetricto one another in the column direction CD centering on the detectingtransistor TA3, respectively. The detecting transistor TA3 may bearranged to be surrounded by the read transistors TC21 and TC22, theglobal read gates TD21 and TD22, and the global reset transistors TE21and TE22. The cells CE21 and 0E22 may be arranged to be adjacent to eachother in a direction inclined to the column direction C1) at 45°.

An interconnection used to transfer the global reset signal ARSET isconnected to the gate electrodes GE3 and GE4, an interconnection used totransfer the global read signal ARead is connected to the gateelectrodes GD3 and GD4, an interconnection used to transfer the resetpotential VReset is connected to the impurity diffusion layer FH52, aninterconnection used to transfer the power potential VDD is connected tothe impurity diffusion layer FH47, an interconnection used to transferthe pixel signal Vsig1 is connected to the impurity diffusion layerFH57, an interconnection used to transfer the read signal Read1 isconnected to the gate electrode GC3, an interconnection used to transferthe read signal Read2 is connected to the gate electrode GC4, and aninterconnection used to transfer the reset signal RESET is connected tothe gate electrode GB3. The gate electrode GA3 is connected to theimpurity diffusion layer FH51.

Here, since the cells CE21 and CE22 are arranged to be adjacent to eachother, in a direction inclined to the column direction CD at 45°, theinterconnection used to transfer the read signals Read1 and Read2 andthe interconnection used to transfer the reset signal RESET can beshared between the cells CE21 and CE22. Thus, the interconnection usedto transfer the read signals Read1 and Read2 and the interconnectionused to transfer the reset signal RESET need not be separately disposedin the cells CE21 and CE22, and thus the number of interconnections canbe reduced.

FIG. 18 is a cross-sectional view taken along line C1-C2 of FIG. 17.

Referring to FIG. 18, an impurity diffusion layer FH41 is formed at theback surface side of a semiconductor substrate SB3, and an impuritydiffusion layer FH40 is formed on the uppermost layer of the backsurface side of the semiconductor substrate SB3. A P well FH45 is formedon the front surface side of the semiconductor substrate SB3, and a Pwell FH46 is formed in the P well FH45. The P well FH45 may be formed tobe higher in impurity concentration than the P well FH46. The gateelectrodes GB3, GC3, GD3, and GE3 are formed above the P well FH46. Inthe P well FH46, the impurity diffusion layer FH44 is formed between thegate electrodes GE3 and GD3, the impurity diffusion layers FH46, FH48,FH49, and FH50 are formed below the gate electrode GD1, and the impuritydiffusion layer. FH51 is formed between the gate electrodes GC3 and GB3.Further, in the P well FH46, the impurity diffusion layer FH46 is formedat the side opposite to the impurity diffusion layer FH44 with the gateelectrode GE3 interposed therebetween, and the impurity diffusion layerFH52 is formed at the side opposite to the impurity diffusion layer FH51with the gate electrode GB3 interposed therebetween. The impuritydiffusion layers FH43 and FH42 are sequentially formed in the depthdirection between the impurity diffusion layers FH44 and FH41. Theimpurity diffusion layers FH41, FH42, FH43, FH47, FH48, FH49, FH50,FH51, and FH52 may have an n type, and the impurity diffusion layersFH40 and FH44 may have a p type. The impurity diffusion layers FH41,FH42, and FH43 are formed to increase in the impurity concentration inthe described order. The impurity diffusion layers FH48, FH49, and FH50are formed to increase in the impurity concentration in the describedorder. The photoelectric converting layer PA21 may be arranged to atleast partially overlap the charge accumulating layer MA21. Thephotoelectric converting layer PA21 may be separated from the chargeaccumulating layer MA21 by the P well FH45.

On the back surface side of the semiconductor substrate SB3, atransparent layer EL21 is formed on the impurity diffusion layer FH40,and a microlens ML21 is formed over the transparent layer EL21 with acolor filter FL21 interposed therebetween. A light blocking layer SL21is buried in the transparent layer EL21. The microlens ML21 may makelight incident to the back surface side of the semiconductor substrateSB3 to be collected on the photoelectric converting layer PA21 not to beincident to the charge accumulating layer MA21. The light blocking layerSL21 can block light incident to the back surface side of thesemiconductor substrate SB3 from being incident to the chargeaccumulating layer MA21. The transparent layer EL21 increases aninterval between the photoelectric converting layer PA21 and themicrolens ML21, and thus an incident angle of light incident to thephotoelectric converting layer PA21 can be reduced.

Here, as the photoelectric converting layer PA21 is arranged to at leastpartially overlap the charge accumulating layer MA21, the size of thepixel P can be reduced while supporting the global shutter structure.Further, as the light blocking layer SL21 is formed at the back surfaceside of the semiconductor substrate SB3, light incident to the backsurface side of the semiconductor substrate SB3 can be prevented frombeing incident to the charge accumulating layer MA21. Furthermore, asthe transparent layer EL21 is formed at the back surface side of thesemiconductor substrate SB3, an incident angle of light incident to thephotoelectric converting layer PA21 can be reduced, and light to becollected on the photoelectric converting layer PA21 can be preventedfrom leaking to the charge accumulating layer MA21. In addition, as theimpurity diffusion layer FH40 is formed on the uppermost layer of theback surface side of the semiconductor substrate SB3, a leakage currentleaking to the charge accumulating layer MA21 can be reduced.

Further, as the P well in the front surface side of the semiconductorsubstrate SB3 has a dual-layer structure, and the P well FH45 separatingthe photoelectric converting layer PA21 from the charge accumulatinglayer MA21 is higher in the impurity concentration than the P well FH46in which a channel is formed, isolation between the photoelectricconverting layer PA21 and the charge accumulating layer MA21 can beimproved. Further, as the P well FH45 is formed, the capacity of thephotoelectric converting layer PA21 and the charge accumulating layerMA21 can be increased, the number of saturated electrons can beincreased, and charges generated in the boundary between thephotoelectric converting layer PA21 and the charge accumulating layerMA21 can be easily taken into the photoelectric converting layer PA21.

FIG. 19A is a cross-sectional view illustrating a configuration in whichthe impurity diffusion layer of the photoelectric converting layer ofFIG. 18 is developed in the horizontal direction, and FIG. 19B is adiagram illustrating the potential distribution of the configurationillustrated in FIG. 19A.

Referring to FIG. 19A, the impurity diffusion layers FH41, FH42, andFH43 are set to increase in the impurity concentration in the describedorder, and the potential gradient is formed from the back surface sideof the semiconductor substrate SB3 toward the front surface sidethereof. Thus, charges generated at the back surface side of thephotoelectric converting layer PA21 can be collected at the frontsurface side thereof, and charges can be smoothly transferred from thephotoelectric converting layer PA21 to the charge accumulating layerMA21.

FIG. 20 is a circuit diagram illustrating a schematic configuration of atwo-pixel one-cell structure according to an eighth embodiment.

Referring to FIG. 20, a cell includes photoelectric converting layersPA31 and PA32, charge accumulating layers MAA3, MAB3, MAA4, and MAB4, adetecting transistor TA4, a reset transistor TB4, read transistors TCA3,TCB3, TCA4, and TCB4, global reset transistors TE31 and TE32, and globalread gates TDA3, TDB3, TDA4, and TDB4. A floating diffusion FD is formedat a connection point among the detecting transistor TA4, the resettransistor TB4, and the read transistors TCA3, TCB3, TCA4, and TCB4 as adetection node. Here, the photodiodes PD31 and PD32 are formed in thephotoelectric converting layers PA31 and PA32, respectively, and thecharge coupling layers MDA3, MDB3, MDA4, and MDB4 are formed in thecharge accumulating layers MAA3, MAB3, MAA4, and MAB4, respectively.

Here, the photoelectric converting layer PA31, the charge accumulatinglayers MAA3 and MAB3, the read transistors TCA3 and TCB3, the globalreset transistor TE31, and the global read gates TDA3 and TDB3 maybelong to one pixel P of the cell, and the photoelectric convertinglayer. PA32, the charge accumulating layers MAA4 and MAB4, the readtransistors TCA4 and TCB4, the global reset transistor TE32, and theglobal read gates TDA4 and TDB4 may belong to the other pixel P of thecell. The floating diffusion FD, the detecting transistor TA4, and thereset transistor TB4 are shared by the two pixels P of the cell.

The global read gate TDA3 and the read transistor TCA3 are connected inseries, the global read gate TDB3 and the read transistor TCB3 areconnected in series, and the series circuits are connected to the globalreset transistor TE31 in parallel. The photodiode PD31 is connected to aconnection point among the global reset transistor TE31 and the globalread gates TDA3 and TDB3, and the charge coupling layers MDA3 and MDB3are coupled to the global read gates TDA3 and TDB3, respectively.

The global read gate TDA4 and the read transistor TCA4 are connected inseries, the global read gate TDB4 and the read transistor TCB4 areconnected in series, and the series circuits are connected to the globalreset transistor TE41 in parallel. The photodiode PD32 is connected to aconnection point among the global reset transistor TE32 and the globalread gates TDA4 and TDB4, and the charge coupling layers MDA4 and MDB4are coupled to the global read gates TDA4 and TDB4, respectively.

Sources of the read transistors TCA3, TCB3, TCA4, and TCB4, and a gateof the detecting transistor TA4, and a source of the reset transistorTB4 are connected to the floating diffusion FD.

The global reset signal ARSET is input to gates of the global resettransistors TE31 and TE32, the global read signal AReadA is input to theglobal read gates TDA3 and TDA4, and the global read signal AReadB isinput to the global read gates TDB3 and TDB4. The read signals Read1A,Read1B, Read2A, and Read2B are input to gates of the read transistorsTCA3, TCB3, TCA4, and TCB4, respectively, and the reset signal RESET isinput to a gate of the reset transistor TB4. The reset potential VResetis input to a drain of the reset transistor TB4, the power potential VDDis input to a drain of the detecting transistor TA4, and the pixelsignal Vsig is output from a source of the detecting transistor TA4 tothe vertical signal line Vlin.

FIG. 21 is a plane view illustrating the layout structure of thetwo-pixel one-cell structure of FIG. 20.

Referring to FIG. 21, a cell CE31 includes the photoelectric convertinglayers PA31 and PA32, and the charge accumulating layers MAA3, MAB3,MAA4, and MAB4. Here, the photoelectric converting layers PA31 and PA32may be disposed on the back surface side of the semiconductor substrate,and the charge accumulating layers MAA3, MAB3, MAA4, and MAB4 may bedisposed on the front surface side of the semiconductor substrate. Thephotoelectric converting layers PA31 and PA32 may at least partiallyoverlap the charge accumulating layers MAA3, MAB3, MAA4, and MAB4.Microlenses ML31 and ML32 are disposed on the photoelectric convertinglayers PA31 and PA32, respectively. The microlenses ML31 and ML32 maymake light incident to the back surface side of the semiconductorsubstrate to be collected on the photoelectric converting layers PA31and PA32 not to be incident to the charge accumulating layers MAA3,MAB3, MAA4, and MAB4.

Further, the cell CE31 includes gate electrodes GA4, GB4, GCA3, GCB3,GCA4, GCB4, GDA3, GDA4, GDB3, GDB4, GE13, and GE14. The gate electrodesGA4, GB4, GCA3, GCB3, GCA4, GCB4, GDA3, GDA4, GDB3, GDB4, GE13, and GE14may be disposed on the front surface side of the semiconductorsubstrate. The gate electrode GA4 may configure the detecting transistorTA4, the gate electrode GB4 may configure the reset transistor TB4, thegate electrodes GCA3, GCB3, GCA4, and GCB4 may configure the readtransistors TCA3, TCB3, TCA4, and TCB4, respectively, the gateelectrodes GDA3, GDB3, GDA4, and GDB4 may configure the global readgates TDA3, TDB3, TDA4, and TDB4, respectively, and the gate electrodesGE13 and GE14 may configure the global reset transistors TE13 and TE14,respectively.

An impurity diffusion layer FH64 is formed between the gate electrodeGE13 and the gate electrodes GDA3 and GDB4, an impurity diffusion layerFH66 is formed between the gate electrode GDA3 and the gate electrodeGCA3, an impurity diffusion layer FH66 is formed between the gateelectrode GDB3 and the gate electrode GCB3, an impurity diffusion layerFH74 is formed between the gate electrode GE14 and the gate electrodesGDA4 and GDB4, an impurity diffusion layer FH66 is formed between thegate electrode GDA4 and the gate electrode GCA4, an impurity diffusionlayer FH66 is formed between the gate electrode GDB4 and the gateelectrode GCB4, and an impurity diffusion layer FH71 is formed betweenthe gate electrodes GCA3, GCB3, GCA4, and GCB4 and the gate electrodeGB4. An impurity diffusion layer FH67 is formed at the side opposite tothe impurity diffusion layer FH64 with the gate electrode GE13interposed therebetween, an impurity diffusion layer FH73 is formed atthe side opposite to the impurity diffusion layer FH74 with the gateelectrode GE14 interposed therebetween, and an impurity diffusion layerFH72 is formed at the side opposite to the impurity diffusion layer FH71with the gate electrode GB4 interposed therebetween. Impurity diffusionlayers FH78 and FH79 are formed at both sides of the gate electrode GA4.The impurity diffusion layers FH68, FH69, and FH70 are formed below thegate electrode GDA3, the impurity diffusion layers FH78, FH79, and FH80are formed below the gate electrode GDB3, the impurity diffusion layersFH81, FH82, and FH83 are formed below the gate electrode GDA4, and theimpurity diffusion layers FH75, FH76, and FH77 are formed below the gateelectrode GDB4.

Here, the photoelectric converting layers PA31 and PA32 may be arrangedto be symmetrical to each other in the column direction CD centering onthe detecting transistor TA4, and the charge accumulating layers MAA3and MAB3 and the charge accumulating layers MAA4 and MAB4 may bearranged to be symmetrical to each other in the column direction CDcentering on the detecting transistor TA4. The read transistors TCA3,TCB3, TCA4, and TCB4, the global read gates TDA3, TDB3, TDA4, and TDB4,and the global reset transistors TE41 and TE42 may be arranged to besymmetrical to each other in the column direction CD centering on thedetecting transistor TA4, respectively. The gate electrodes GCA3, GCB3,GDA3, and GDB3 may be arranged on sides of a rectangle, respectively,and the gate electrodes GB4 and GE13 may be arranged at facing diagonalpositions of a rectangle, respectively. The gate electrodes GCA4, GCB4,GDA4, and GDB4 may be arranged on sides of a rectangle, respectively,and the gate electrodes GB4 and GE14 may be arranged at facing diagonalpositions of a rectangle, respectively. The cells CE31 and CE32 may bearranged to be adjacent to each other in a direction inclined to thecolumn direction CD at 45°.

An interconnection used to transfer the global reset signal ARSET isconnected to the gate electrodes GE13 and GE14, an interconnection usedto transfer the global read signal AReadA is connected to the gateelectrodes GDA3 and GDA4, an interconnection used to transfer the globalread signal AReadB is connected to the gate electrodes GDB3 and GDB4, aninterconnection used to transfer the reset potential VReset is connectedto the impurity diffusion layer FH72, an interconnection used totransfer the power potential VDD is connected to the impurity diffusionlayers FH67 and FH73, an interconnection used to transfer the pixelsignal Vsig2 is connected to the impurity diffusion layer FH78, aninterconnection used to transfer the read signal Read1A is connected tothe gate electrode GCA3, an interconnection used to transfer the readsignal Read1B is connected to the gate electrode GCB3, aninterconnection used to transfer the read signal Read2A is connected tothe gate electrode GCA4, an interconnection used to transfer the readsignal Read2B is connected to the gate electrode GCB4, and aninterconnection used to transfer the reset signal RESET is connected tothe gate electrode GB2. The gate electrode GA24 is connected to theimpurity diffusion layer FH71.

Here, since the cells CE31 and CE32 are arranged to be adjacent to eachother in a direction inclined to the column direction CD at 45′, theinterconnection used to transfer the read signals Read1A, Read1B,Read2A, and Read2B and the interconnection used to transfer the resetsignal. RESET can be shared between the cells CE31 and CE32. Thus, theinterconnection used to transfer the read signals Read1A, Read1B,Read2A, and Read2B and the interconnection used to transfer the resetsignal RESET need not be separately disposed in the cells CE31 and CE32,and thus the number of interconnections can be reduced.

FIG. 22 is a cross-sectional view taken along line D1-D2 of FIG. 21.

Referring to FIG. 22, an impurity diffusion layer FH61 is formed at theback surface side of a semiconductor substrate SB4, and an impuritydiffusion layer FH60 is formed on the uppermost layer of the backsurface side of the semiconductor substrate SB4. A P well. FH65 isformed on the front surface side of the semiconductor substrate SB4, anda P well FH66 is formed in the P well FH65. The P well FH65 may beformed to be higher in impurity concentration than the P well FH66. Thegate electrodes GB4, GCA3, GDA3, and GE13 are formed above the P wellFH66. In the P well FH46, the impurity diffusion layer. FH64 is formedbetween the gate electrodes GE13 and GDA3, the impurity diffusion layerFH66 is formed between the gate electrodes GDA3 and GCA3, and theimpurity diffusion layer FH71 is formed between the gate electrodes GCA3and GB4. Further, in the P well FH46, the impurity diffusion layer FH67is formed at the side opposite to the impurity diffusion layer FH64 withthe gate electrode GE13 interposed therebetween, and the impuritydiffusion layer FH72 is formed at the side opposite to the impuritydiffusion layer FH71 with the gate electrode GB4 interposedtherebetween. The impurity diffusion layers FH63 and FH62 aresequentially formed in the depth direction between the impuritydiffusion layers FH64 and FH61. The impurity diffusion layers FH61,FH62, FH63, FH67, FH68, FH69, FH70, FH71, and FH72 may have an n type,and the impurity diffusion layers FH60 and FH64 may have a p type. Theimpurity diffusion layers FH61, FH62, and FH63 are formed to increase inthe impurity concentration in the described order. The impuritydiffusion layers FH68, FH69, and FH70 are formed to increase in theimpurity concentration in the described order. The photoelectricconverting layer PA31 may be arranged to at least partially overlap thecharge accumulating layer MAA3. The photoelectric converting layer PA31may be separated from the charge accumulating layer MAA3 by the P wellPH65.

On the back surface side of the semiconductor substrate SB4, thetransparent layer EL31 is formed on the impurity diffusion layer FH60,and a microlens ML31 is formed over the transparent layer EL31 with acolor filter FL31 interposed therebetween. The light blocking layer SL31is buried in the transparent layer EL31. The microlens ML31 may makelight incident to the back surface side of the semiconductor substrateSB4 to be collected on the photoelectric converting layer PA31 not to beincident to the charge accumulating layer MAA3. The light blocking layerSL31 can block light incident to the back surface side of thesemiconductor substrate SB4 from being incident to the chargeaccumulating layer MAA3. The transparent layer EL31 increases aninterval between the photoelectric converting layer PA31 and themicrolens ML31, and thus an incident angle of light incident to thephotoelectric converting layer PA31 can be reduced.

Here, as the photoelectric converting layer PA31 is arranged to at leastpartially overlap the charge accumulating layer MAA3, the size of thepixel P can be reduced while supporting the global shutter structure.Further, as the light blocking layer SL31 is formed at the back surfaceside of the semiconductor substrate SB4, light incident to the backsurface side of the semiconductor substrate SB4 can be prevented frombeing incident to the charge accumulating layer MAA3. Furthermore, asthe transparent layer EL31 is formed at the back surface side of thesemiconductor substrate SB4, an incident angle of light incident to thephotoelectric converting layer PA31 can be reduced, and light to becollected on the photoelectric converting layer PA31 can be preventedfrom leaking to the charge accumulating layer MAA3. In addition, as theimpurity diffusion layer FH60 is formed on the uppermost layer of theback surface side of the semiconductor substrate SB4, a leakage currentleaking to the charge accumulating layer MAA3 can be reduced.

Further, as the P well in the front surface side of the semiconductorsubstrate SB4 has a dual-layer structure, and the P well FH45 separatingthe photoelectric converting layer PA31 from the charge accumulatinglayer MAA3 is higher in the impurity concentration than the P well FH46in which a channel is formed, isolation between the photoelectricconverting layer PA31 and the charge accumulating layer MAA3 can beimproved. Further, as the P well FH45 is formed, the capacity of thephotoelectric converting layer PA31 and the charge accumulating layerMAA3 can be increased, the number of saturated electrons can beincreased, and charges generated in the boundary between thephotoelectric converting layer PA31 and the charge accumulating layerMAA3 can be easily taken into the photoelectric converting layer PA31.

The potential distribution of the impurity diffusion layers of thephotoelectric converting layer and the charge accumulating layer of FIG.22 is the same as in FIG. 19B. Here, the impurity diffusion layersF1161, FH62, and FH63 are set to increase in the impurity concentrationin the described order, and the potential gradient is formed from theback surface side of the semiconductor substrate SB4 toward the frontsurface side thereof. Thus, charges generated at the back surface sideof the photoelectric converting layer PA31 can be collected at the frontsurface side thereof, and charges can be smoothly transferred from thephotoelectric converting layer PA31 to the charge accumulating layerMAA3.

The above embodiments have been described in connection with the exampleof the two-pixel one-cell structure, but may be applied to anotherstructure such as a one-pixel one-cell structure or a four-pixelone-cell structure. Further, the above embodiments have been describedin connection with the method of performing row selection without usingan address transistor performing row selection, but an addresstransistor performing row selection may be disposed in each cell.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A solid-state imaging device, comprising: aphotoelectric converting layer that is formed at a back surface side ofa semiconductor substrate, and photoelectric-converts and accumulatescharges; a reading unit that is formed at a front surface side of thesemiconductor substrate, and reads out the accumulated charges by thephotoelectric converting layer; a charge accumulating layer that isformed at the front surface side of the semiconductor substrate, andaccumulates charges read out by the reading unit; a light blocking layerthat blocks light incident to the back surface side of the semiconductorsubstrate from being incident to the charge accumulating layer; atransparent layer formed on the light blocking layer; and a lightcollecting unit that is formed on the transparent layer, and makes lightincident to the back surface side of the semiconductor substrate to becollected on the photoelectric converting layer.
 2. The solid-stateimaging device according to claim 1, wherein the photoelectricconverting layer is arranged to at least partially overlap the chargeaccumulating layer.
 3. The solid-state imaging device according to claim1, wherein charge accumulation operations of the photoelectricconverting layers of all pixels are simultaneously started, and chargesare simultaneously read out from the photoelectric converting layers ofall pixels to the charge accumulating layer.
 4. The solid-state imagingdevice according to claim 1, further comprising: a global resettransistor that simultaneously resets the photoelectric convertinglayers of all pixels; a global read transistor that simultaneouslytransfers charges from the photoelectric converting layers of all pixelsto the charge accumulating layer; a read transistor that reads out thecharges transferred to the charge accumulating layer to a floatingdiffusion of each pixel; a detecting transistor that detects the chargesread out to the floating diffusion; and a reset transistor that resetsthe floating diffusion.